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improved expansion bus cpyr handling

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This commit is contained in:
JJ Bliss
2026-05-06 16:54:11 -04:00
parent a98819e759
commit 789e72ba55
1 changed files with 23 additions and 15 deletions
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uxn/uxn.ha
+23 -15
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@@ -172,6 +172,11 @@ export fn emu_deo(port: u8, value: u8, state: *uxn) void = {
// fmt::printfln("Writing {:x} to port {:x}", value, port)!; // fmt::printfln("Writing {:x} to port {:x}", value, port)!;
state.dev[port] = value; state.dev[port] = value;
switch(port) { switch(port) {
case 0x03 =>
const high = state.dev[0x02];
const low = value;
const eaddr = short_from_bytes(high,low);
deo_expansion(eaddr,state);
case 0x04 => case 0x04 =>
state.ptr[0] = value; state.ptr[0] = value;
case 0x05 => case 0x05 =>
@@ -179,8 +184,8 @@ export fn emu_deo(port: u8, value: u8, state: *uxn) void = {
case 0x0e => case 0x0e =>
print_stack_debug(state); print_stack_debug(state);
case 0x11 => case 0x11 =>
let high = state.dev[0x10]; const high = state.dev[0x10];
let low = value; const low = value;
state.console_vector = short_from_bytes(high,low); state.console_vector = short_from_bytes(high,low);
// fmt::printfln("Setting console_vector to: {:x}", console_vector)!; // fmt::printfln("Setting console_vector to: {:x}", console_vector)!;
case 0x18 => case 0x18 =>
@@ -246,29 +251,32 @@ fn deo_expansion(addr: u16, state: *uxn) void = {
const length = short_from_bytes(state.ram[addr+1],state.ram[addr+2]); const length = short_from_bytes(state.ram[addr+1],state.ram[addr+2]);
switch(op) { switch(op) {
case 0x00 => //fill case 0x00 => //fill
const bank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]); const bank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]): u32;
const addr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]); const addr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]): u32;
const value = state.ram[addr+7]; const value = state.ram[addr+7];
fmt::printfln("expansion fill: bank: {:x} addr: {:x} value: {:x} | length: {:x}",bank,addr,value,length)!;
if(bank < numbanks) for(let i: u16 =0; i < length; i+=1){ if(bank < numbanks) for(let i: u16 =0; i < length; i+=1){
state.ram[bank * banksize + addr + i] = value; state.ram[bank * banksize + addr + i] = value;
}; };
case 0x01 => //cpyl case 0x01 => //cpyl
const srcbank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]); const srcbank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]): u32;
const srcaddr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]); const srcaddr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]): u32;
const dstbank = short_from_bytes(state.ram[addr+7],state.ram[addr+8]); const dstbank = short_from_bytes(state.ram[addr+7],state.ram[addr+8]): u32;
const dstaddr = short_from_bytes(state.ram[addr+9],state.ram[addr+10]); const dstaddr = short_from_bytes(state.ram[addr+9],state.ram[addr+10]): u32;
fmt::printfln("Cpyl: src: {:x} <-> {:x} dst: {:x} <-> {:x} | length: {:x}",srcbank,srcaddr,dstbank,dstaddr,length)!;
if(srcbank < numbanks && dstbank < numbanks) for(let i: u16 =0; i < length; i+=1){ if(srcbank < numbanks && dstbank < numbanks) for(let i: u16 =0; i < length; i+=1){
const readval = state.ram[srcbank * banksize + srcaddr + i]; const readval = state.ram[srcbank * banksize + srcaddr + i];
state.ram[dstbank * banksize + dstaddr + i] = readval; state.ram[dstbank * banksize + dstaddr + i] = readval;
}; };
case 0x02 => //cpr TODO are these actually different?? Either way need to not use for loop case 0x02 => //cpr TODO are these actually different?? Either way need to not use for loop
const srcbank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]); const srcbank = short_from_bytes(state.ram[addr+3],state.ram[addr+4]): u32;
const srcaddr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]); const srcaddr = short_from_bytes(state.ram[addr+5],state.ram[addr+6]): u32;
const dstbank = short_from_bytes(state.ram[addr+7],state.ram[addr+8]); const dstbank = short_from_bytes(state.ram[addr+7],state.ram[addr+8]): u32;
const dstaddr = short_from_bytes(state.ram[addr+9],state.ram[addr+10]); const dstaddr = short_from_bytes(state.ram[addr+9],state.ram[addr+10]): u32;
if(srcbank < numbanks && dstbank < numbanks) for(let i: u16 =0; i < length; i+=1){ fmt::printfln("Cpyr: src: {:x} <-> {:x} dst: {:x} <-> {:x} | length: {:x}",srcbank,srcaddr,dstbank,dstaddr,length)!;
const readval = state.ram[srcbank * banksize + srcaddr + i]; if(srcbank < numbanks && dstbank < numbanks) for(let i: u16 =1; i <= length; i+=1){
state.ram[dstbank * banksize + dstaddr + i] = readval; const readval = state.ram[srcbank * banksize + srcaddr + length - i];
state.ram[dstbank * banksize + dstaddr + length - i] = readval;
}; };
case => case =>
fmt::fatalf("Unknown expansion op: 0x{:x}",op); fmt::fatalf("Unknown expansion op: 0x{:x}",op);